iverilog - Verilog simulation and synthesis tool

Property Value
Distribution FreeBSD 12
Repository FreeBSD Ports Latest amd64
Package filename iverilog-10.3.txz
Package name iverilog
Package version 10.3
Package release -
Package architecture amd64
Package type txz
Category cad
Homepage http://iverilog.icarus.com/
License GPLv2
Maintainer zeising@FreeBSD.org
Download size 1.62 MB
Installed size 5.89 MB
Icarus Verilog is a Verilog simulation and synthesis tool. It
operates as a compiler, compiling source code written in Verilog
(IEEE-1364) into some target format. For batch simulation, the
compiler can generate C++ code that is compiled and linked with
a run time library (called "vvm") then executed as a command to
run the simulation. For synthesis, the compiler generates netlists
in the desired format.
The compiler proper is intended to parse and elaborate design
descriptions written to the IEEE standard IEEE Std 1364-2000. The
standard proper is due to be release towards the middle of the
year 2000. This is a fairly large and complex standard, so it will
take some time for it to get there, but that's the goal.
WWW: http://iverilog.icarus.com/


Package Version Architecture Repository
iverilog-10.3.txz 10.3 i386 FreeBSD Ports Latest
iverilog-10.3.txz 10.3 i386 FreeBSD Ports Quarterly
iverilog-10.3.txz 10.3 amd64 FreeBSD Ports Quarterly
iverilog - - -


Name Value
libhistory.so.8 -
libreadline.so.8 -
readline = 8.0.0


Type URL
Mirror pkg.freebsd.org
Binary Package iverilog-10.3.txz
Source Package cad/iverilog

Install Howto

Install iverilog txz package:

# pkg install iverilog

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